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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICR_ISPENDR0, Interrupt Set-Pending Register 0</h1><p>The GICR_ISPENDR0 characteristics are:</p><h2>Purpose</h2>
        <p>Adds the pending state to the corresponding SGI or PPI.</p>
      <h2>Configuration</h2>
        <p>A copy of this register is provided for each Redistributor.</p>
      <h2>Attributes</h2>
        <p>GICR_ISPENDR0 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit31</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit30</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit29</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit28</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit27</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit26</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit25</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit24</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit23</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit22</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit21</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit20</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit19</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit18</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit17</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit16</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit14</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">Set_pending_bit0</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">Set_pending_bit&lt;x&gt;, bit [x], for x = 31 to 0</h4><div class="field">
      <p>For PPIs and SGIs, adds the pending state to interrupt number x. Reads and writes have the following behavior:</p>
    <table class="valuetable"><tr><th>Set_pending_bit&lt;x&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>If read, indicates that the corresponding interrupt is not pending on this PE.</p>
<p>If written, has no effect.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>If read, indicates that the corresponding interrupt is pending, or active and pending on this PE.</p>
<p>If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending. This has no effect in the following cases:</p>
<ul>
<li>If the interrupt is already pending because of a write to <a href="ext-gicr_ispendr0.html">GICR_ISPENDR0</a>.
</li><li>If the interrupt is already pending because the corresponding interrupt signal is asserted. In this case, the interrupt remains pending if the interrupt signal is deasserted.
</li></ul></td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a GIC reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing GICR_ISPENDR0</h2>
        <p>When affinity routing is not enabled for the Security state of an interrupt in GICR_ISPENDR0, the corresponding bit is RAZ/WI and equivalent functionality is provided by <a href="ext-gicd_ispendrn.html">GICD_ISPENDR&lt;n&gt;</a> with n=0.</p>

      
        <p>This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by <a href="ext-gicd_ispendrn.html">GICD_ISPENDR&lt;n&gt;</a>.</p>

      
        <p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.</p>
      <h4>GICR_ISPENDR0 can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Redistributor</td><td>SGI_base</td><td><span class="hexnumber">0x0200</span></td><td>GICR_ISPENDR0</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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